JEDEC releases new standard for low-power memory in mobile devices
Memory industry standards body JEDEC Solid State Technology Association has announced the publication of JESD209-2 LPDDR2 Low Power Memory Device Standard. The new standard offers advanced power management features, a shared interface for nonvolatile memory (NVM) and volatile memory (SDRAM), and a range of densities and speeds. JEDEC believes the the standard will enhance the design of such products as smartphones, cell phones, PDAs, GPS units, handheld gaming consoles, and other mobile devices by enabling increased memory density, improved performance, smaller size, overall reduction in power consumption as well as longer battery life.
The JEDEC LPDDR2 standard offers several power-saving features, including a reduced interface voltage of 1.2V from the 1.8V specification in the previous (LPDDR) memory technology. The standard further encompasses devices having a core voltage of 1.2V (as compared to existing 1.8V core voltage devices). LPDDR2 also supports mechanisms for managing power usage such as Partial Array Self Refresh and Per-Bank Refresh. Partial Array Self-Refresh, for example, allows portions of the array to be powered down when not required, permitting applications to determine device memory requirements on a real-time usage basis.
In addition, for the first time, a single JEDEC standard encompasses two distinct types of memory: NVM and SDRAM. The JEDEC LPDDR2 standard allows these two memory types to share a common bus interface, thereby reducing the controller pincount and facilitating increased memory package density. LPDDR2 NVM and SDRAM devices can be stacked, with a common interface, greatly simplifying memory controller and interface designs and offering space-saving opportunities to product developers.
Multiple device configurations are also supported to meet the requirements of a wide array of mobile devices, including an operating frequency range from 100MHz to 533MHz; data widths of x8, x16 and x32; two pre-fetch options (2bit and 4bit) as well as both 1.8V and 1.2V core voltage options.
According to Nokia, the new standard should, over time, replace today's mobile execution memory solutions like PSRAM, LPDDR1 and Mux NOR flash. Other memory industry players, including Elpida Memory, Numonyx and Spansion also voiced their approval of the new standard.
The JEDEC LPDDR2 standard offers several power-saving features, including a reduced interface voltage of 1.2V from the 1.8V specification in the previous (LPDDR) memory technology. The standard further encompasses devices having a core voltage of 1.2V (as compared to existing 1.8V core voltage devices). LPDDR2 also supports mechanisms for managing power usage such as Partial Array Self Refresh and Per-Bank Refresh. Partial Array Self-Refresh, for example, allows portions of the array to be powered down when not required, permitting applications to determine device memory requirements on a real-time usage basis.
In addition, for the first time, a single JEDEC standard encompasses two distinct types of memory: NVM and SDRAM. The JEDEC LPDDR2 standard allows these two memory types to share a common bus interface, thereby reducing the controller pincount and facilitating increased memory package density. LPDDR2 NVM and SDRAM devices can be stacked, with a common interface, greatly simplifying memory controller and interface designs and offering space-saving opportunities to product developers.
Multiple device configurations are also supported to meet the requirements of a wide array of mobile devices, including an operating frequency range from 100MHz to 533MHz; data widths of x8, x16 and x32; two pre-fetch options (2bit and 4bit) as well as both 1.8V and 1.2V core voltage options.
According to Nokia, the new standard should, over time, replace today's mobile execution memory solutions like PSRAM, LPDDR1 and Mux NOR flash. Other memory industry players, including Elpida Memory, Numonyx and Spansion also voiced their approval of the new standard.
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