ARC® 700 Core Family
Power-Efficient, High Performance 32-Bit Configurable CPU Cores
ARC® 700 configurable cores deliver the computing power needed by demanding system-on-chip (SoC) tasks like graphics and packet processing, with low power consumption. They are also ideal platforms for high-end embedded OSs, such as Linux.
The family comprise the following three members:
* ARC 710D Core (pdf)
* ARC 725D Core (pdf)
* ARC 750D Core (pdf)
Benefits of the 700 Core Family
Fast
In a 40nm process, the ARC 700 cores run at up to 1.2 GHz delivering CPU performance of 1800 DMIPS. Configuration enhancements such as floating point and DSP acceleration produce a core that can satisfy any processing requirement—from hard real-time systems to host implementations running high-level OS and application software.
Flexible
ARC's unique configurable architecture allows the designer to choose exactly which function blocks are needed within the core, and their characteristics. ARC 700 cores can even include custom CPU instructions, providing the perfect fit to any application.
Lean
Selecting only the processor features required results in smaller die size, lower power consumption and lower overall cost than is possible with rival "fixed architecture" cores.
Efficient
A core that fits the application enables designers to achieve more within the tight resource restrictions of an embedded system. ARC cores allow zero-overhead switching between 16-bit and 32-bit instruction sets, reducing external memory footprint.
Easy
ARC cores are made for real-life use, by real-life designers. A full range of ARC proprietary and third-party tools assists development of hardware and software, and genuine co-design. IP blocks, RTOSs and run-time software, all come together to speed the time-to-market of end products.
ARC 700 Core Applications
ARC 700 Cores Family Product Roadmap
ARC® 700 Architecture
CPU Architecture
ARC 700 Series configurable processors employ a 32-bit architecture with a highly efficient seven-stage pipeline, delivering an industry-leading combination of small die size, low power consumption and performance of over 1.5 DMIPS/MHz.
Designed for a wide range of embedded processing applications, the ARC 700 series architecture includes options such as integrated timers, interrupt controllers and bit manipulation instructions. It features built-in inter-processor communications capabilities to facilitate multi-core architectures.
And like all ARC cores, it uses the ARCompact™ ISA (instruction set architecture), allowing 16- and 32-bit instructions to be freely mixed without overhead, to deliver memory footprint savings of up to 40%.
Highly Configurable
ARC's concept of configurability allows optimization of core designs on three distinct levels, within a single, coherent architecture. First, designers can choose the required execution blocks: for instance cache, FPU and DSP. Second, they can tune the parameters of those blocks: for instance, cache size and CPU register file size. Finally, they can define custom instructions, additional core and auxiliary registers, custom condition codes and co-processor interfaces.
In addition to performance, size, power and cost trade-offs, the ARC configurable architecture therefore delivers unrivalled design flexibility. The ARC 700 series cores can also be configured with a variety of external interfaces, including native implementations of BVCI, AHB or AXI. A number of flexible memory options include single-cycle closely coupled memories (CCMs) for instructions and data; configurable instruction and data cache; and a memory management unit (MMU).
Customized Instruction Extensions
In common with all of ARC's configurable cores, the 700 series cores offer designers the opportunity to define custom instructions to accelerate critical parts of their applications. The resultant gains can be used to improve performance by as much as 100 times, to reduce required clock frequencies, or to free up other core resources and increase application flexibility. Other user-defined extensions may include co-processor interfaces, auxiliary registers, and condition codes.
Powerful DSP Capabilities
The 700 series includes powerful options that enable the core to perform DSP functions, without the need to add separate execution blocks or co-processors. These are implemented within the RISC pipeline, with performance of up to 1.9GMACS in a 40nm process. ARC 700 DSP options include 16- and 32-bit MAC and saturating arithmetic instructions. ARC XY Advanced DSP adds configurable banks of XY memory that can be used to facilitate even more complex functions such as dual FFT and Viterbi algorithms.
Floating Point Instructions
ARC™ FPX Floating Point Extensions add high performance single- and double-precision floating point capabilities to the 700 series CPU itself, substantially accelerating execution with little increase in power consumption or die size. These IEEE-compliant instructions and library functions provide the power required for graphics and image processing routines, complex computations or advanced control algorithms.By making use of the main processor pipeline and data paths, FPX extensions can be built with as few as 13K gates. As a result FPX is over five times more efficient in terms of gate usage than typical FPU co-processors.
Software Development
ARC 700 Cores are Supported by the Industry's Leading Development Environments:
* The ARC MetaWare Development Toolkit, including C/C++ compiler, advanced debugger, integrated profiler and Eclipse IDE
* GNU suite, including gcc and gdb
* Green Hills Software Multi Suite
Modeling Tools
ARC provides a wide range of modeling tools to allow software development to begin as soon as the core hardware configuration has been defined.
* ARC xCAM enables the ARChitect IP Configurator to automatically generate cycle accurate models within minutes of a configuration being finalized. Executing at between 40kHz to 60kHz, xCAM models enable a genuinely iterative design approach compatible with SystemC.
* The xISS Turbo instruction set simulator runs at up to 200MHz, enabling fast development, software test and debug. Functionally accurate, xISS is designed to enable software development when hardware is unavailable: for instance prior to first silicon, or when cost or supply issues restrict the availability of prototypes or emulation hardware.
On-Chip Debug Features
Each core's JTAG interface allows a debug host to set software breakpoints, examine or change memory and register values, and step through the target code. Optional hardware breakpoints can be added.
Operating Systems
The ARC 700 family is supported by industry standard operating system software from ARC and from third parties:
* ARC MQX RTOS
* Embedded Linux
* Express Logic ThreadX RTOS
* Micrium μC/OS-II
* μITRON
ARC® 700 configurable cores deliver the computing power needed by demanding system-on-chip (SoC) tasks like graphics and packet processing, with low power consumption. They are also ideal platforms for high-end embedded OSs, such as Linux.
The family comprise the following three members:
* ARC 710D Core (pdf)
* ARC 725D Core (pdf)
* ARC 750D Core (pdf)
Benefits of the 700 Core Family
Fast
In a 40nm process, the ARC 700 cores run at up to 1.2 GHz delivering CPU performance of 1800 DMIPS. Configuration enhancements such as floating point and DSP acceleration produce a core that can satisfy any processing requirement—from hard real-time systems to host implementations running high-level OS and application software.
Flexible
ARC's unique configurable architecture allows the designer to choose exactly which function blocks are needed within the core, and their characteristics. ARC 700 cores can even include custom CPU instructions, providing the perfect fit to any application.
Lean
Selecting only the processor features required results in smaller die size, lower power consumption and lower overall cost than is possible with rival "fixed architecture" cores.
Efficient
A core that fits the application enables designers to achieve more within the tight resource restrictions of an embedded system. ARC cores allow zero-overhead switching between 16-bit and 32-bit instruction sets, reducing external memory footprint.
Easy
ARC cores are made for real-life use, by real-life designers. A full range of ARC proprietary and third-party tools assists development of hardware and software, and genuine co-design. IP blocks, RTOSs and run-time software, all come together to speed the time-to-market of end products.
ARC 700 Core Applications
ARC 700 Cores Family Product Roadmap
ARC® 700 Architecture
CPU Architecture
ARC 700 Series configurable processors employ a 32-bit architecture with a highly efficient seven-stage pipeline, delivering an industry-leading combination of small die size, low power consumption and performance of over 1.5 DMIPS/MHz.
Designed for a wide range of embedded processing applications, the ARC 700 series architecture includes options such as integrated timers, interrupt controllers and bit manipulation instructions. It features built-in inter-processor communications capabilities to facilitate multi-core architectures.
And like all ARC cores, it uses the ARCompact™ ISA (instruction set architecture), allowing 16- and 32-bit instructions to be freely mixed without overhead, to deliver memory footprint savings of up to 40%.
Highly Configurable
ARC's concept of configurability allows optimization of core designs on three distinct levels, within a single, coherent architecture. First, designers can choose the required execution blocks: for instance cache, FPU and DSP. Second, they can tune the parameters of those blocks: for instance, cache size and CPU register file size. Finally, they can define custom instructions, additional core and auxiliary registers, custom condition codes and co-processor interfaces.
In addition to performance, size, power and cost trade-offs, the ARC configurable architecture therefore delivers unrivalled design flexibility. The ARC 700 series cores can also be configured with a variety of external interfaces, including native implementations of BVCI, AHB or AXI. A number of flexible memory options include single-cycle closely coupled memories (CCMs) for instructions and data; configurable instruction and data cache; and a memory management unit (MMU).
Customized Instruction Extensions
In common with all of ARC's configurable cores, the 700 series cores offer designers the opportunity to define custom instructions to accelerate critical parts of their applications. The resultant gains can be used to improve performance by as much as 100 times, to reduce required clock frequencies, or to free up other core resources and increase application flexibility. Other user-defined extensions may include co-processor interfaces, auxiliary registers, and condition codes.
Powerful DSP Capabilities
The 700 series includes powerful options that enable the core to perform DSP functions, without the need to add separate execution blocks or co-processors. These are implemented within the RISC pipeline, with performance of up to 1.9GMACS in a 40nm process. ARC 700 DSP options include 16- and 32-bit MAC and saturating arithmetic instructions. ARC XY Advanced DSP adds configurable banks of XY memory that can be used to facilitate even more complex functions such as dual FFT and Viterbi algorithms.
Floating Point Instructions
ARC™ FPX Floating Point Extensions add high performance single- and double-precision floating point capabilities to the 700 series CPU itself, substantially accelerating execution with little increase in power consumption or die size. These IEEE-compliant instructions and library functions provide the power required for graphics and image processing routines, complex computations or advanced control algorithms.By making use of the main processor pipeline and data paths, FPX extensions can be built with as few as 13K gates. As a result FPX is over five times more efficient in terms of gate usage than typical FPU co-processors.
Software Development
ARC 700 Cores are Supported by the Industry's Leading Development Environments:
* The ARC MetaWare Development Toolkit, including C/C++ compiler, advanced debugger, integrated profiler and Eclipse IDE
* GNU suite, including gcc and gdb
* Green Hills Software Multi Suite
Modeling Tools
ARC provides a wide range of modeling tools to allow software development to begin as soon as the core hardware configuration has been defined.
* ARC xCAM enables the ARChitect IP Configurator to automatically generate cycle accurate models within minutes of a configuration being finalized. Executing at between 40kHz to 60kHz, xCAM models enable a genuinely iterative design approach compatible with SystemC.
* The xISS Turbo instruction set simulator runs at up to 200MHz, enabling fast development, software test and debug. Functionally accurate, xISS is designed to enable software development when hardware is unavailable: for instance prior to first silicon, or when cost or supply issues restrict the availability of prototypes or emulation hardware.
On-Chip Debug Features
Each core's JTAG interface allows a debug host to set software breakpoints, examine or change memory and register values, and step through the target code. Optional hardware breakpoints can be added.
Operating Systems
The ARC 700 family is supported by industry standard operating system software from ARC and from third parties:
* ARC MQX RTOS
* Embedded Linux
* Express Logic ThreadX RTOS
* Micrium μC/OS-II
* μITRON
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